1. Field of the Invention
The present invention relates generally to a programmable logic LSI and a two-dimensional array. More particularly, the invention relates to a two-dimensional array, in which base cells are connected with each other, forming a programmable logic LSI, such as field programmable gate array (FPGA) and so forth.
2. Description of the Related Art
A programmable logic LSI, typically an FPGA, is an LSI which internally holds a configuration information designating how a hardware is configured, and realizes a desired hardware according to designation of the configuration information. In the recent years, associating with expansion of scale of hardware which can be realized by the programmable logic LSI owing to progress of semiconductor fabrication technologies, replacement from gate array LSIs to the programmable logic LSIs is in progress and is attracting attention.
Elements forming the programmable logic LSI are three elements constituted of logic cells, wiring cells and external input and output cells. The logic cell has a function for realizing arbitrary logical operation, such as four input and one output, according to designation of the configuration information. The wiring cell has a function connecting an output of a certain logic cell and an input of another logic cell, for example, according to designation of the configuration information. On the other hand, the external input and output cell executes inputting and outputting signals from and to outside of the programmable logic LSI. Feature of the programmable logic LSI is determined by how the three elements are arranged and how mutually connection is established. It should be noted that the present invention concerns construction of the logic cell and the wiring cell among the foregoing three elements and array structure thereof. Therefore, discussion for the external input and output cell will be neglected from the following disclosure in order to avoid complication of disclosure by including discussion of unnecessary element and to keep the disclosure simple enough to facilitate clear understanding of the present invention.
Here, construction of the conventional programmable logic LSI can be generally classified into two types. One type is that disclosed in U.S. Pat. No. 4,870,302, for xe2x80x9cConfigurable Electrical Circuit having Configurable Logic Elements and Configurable Interconnectsxe2x80x9d owned by Xilinx, Inc. and Re-Issue Pat. No. 34,363 as reissue patent of the former, which will be referred to hereinafter as first prior art. The other type is that disclosed in U.S. Pat. No. 5,155,389, for xe2x80x9cProgrammable Logic Cell and Arrayxe2x80x9d, owned by Concurrent Logic, Inc, which will be referred to hereinafter as second prior art.
In the first prior art, as can be clear from the title of the invention, there has been disclosed a method for realizing a programmable logic LSI by combination of re-configurable, namely programmable logic cell and re-configurable, namely programmable wiring cell. Namely, the programmable logic LSI is formed by arranging sets of the logic cells and the wiring cells in a two-dimensional array.
Next, in the second prior art, there has been disclosed a method for realizing the programmable LSI with uniform two-dimensional array of the programmable logic cells. In this second prior art, respective logic cells are directly connected to adjacent four logic cells with single direction wiring. The feature of the second prior art is that the logic cells thus connected serve as the wiring cells. Accordingly, in the second prior art, there is no wiring cell, basically.
The first prior art is advantageous in that the logic cell and the wiring cell can be optimized adapting to the tasks thereof. However, the first prior art holds shortcoming in that a ratio of logical resource and wiring resource is physically fixed in the programmable logic LSI. In general, there are wide variety of circuits to be realized by users on the programmable logic LSI, wherein some require large logical resource but a little wiring resource, such as data path or so forth, another some require large wiring resource but a little logical resource, such as bus or so forth. Therefore, if the ratio of physical logical resource and the wiring resource is fixed, certain amount of wiring resource becomes extra, namely not used, in realization of some circuit, and, in another case, certain amount of the logical resource becomes extra, namely not used, in realization of another circuit. This program is significant and critical in the first prior art.
The second prior art, different from the first prior art, the shortcoming as held by the first prior art will never be encountered since the logic cells realize the function of the wiring cells. However, the wiring utilizing the logical cell as that in the second embodiment encounters a program in flexibility of the wiring. The reason is that this technology realizes the function as the wiring cell by extending the basic function of the logic cell.
More particularly, in the second prior art, the logical cell is constructed as four input and four output. Then, the function as the wiring cell is realized by simply designating connecting between the input for the logic cell and the output thereof without internally performing logical operation. Accordingly, the second prior art may establish only connection between connection lines of single direction which is fixed propagating direction of the signal. Therefore, the second prior art cannot establish connection between bi-directional connection lines which are required for forming bi-directional bus or so forth.
In addition, Japanese Unexamined Patent Publication No. Heisei 10-93422 discloses similar circuit which can establish only connection between connection lines of single direction for fixed signal propagating direction and cannot establish connection between bi-directional connection lines necessary for forming the bi-directional bus or so forth.
The present invention has been worked out in view of the drawbacks in the prior arts as set forth above. Therefore, it is the first object of the present invention to provide as base cell for a programmable logic LSI and a two-dimensional array of the base cells, which can resolve the shortcoming of the foregoing first prior art in that a ratio of wiring resource and logical resource is fixed and can be variable of the ratio of the wiring resource and the logical resource adapting to a circuit construction to be realized.
The second object of the present invention is to provide a base cell for a programmable logic LSI and a two-dimensional array of the base cells, which can accomplish the foregoing first object to realize a circuit which is efficient and has various mutually distinct features.
According to the first aspect of the present invention, a base call for a programmable logic LSI which is formed by connecting a plurality of the base cells, comprises:
a combined programmable circuit realizing a programmable logic circuit function and a programmable wiring circuit function; and
a mode setting circuit for selectively making one of the programmable logic circuit function and the programmable wiring circuit function according to a mode information.
In the construction set forth above, the mode setting circuit may have a mode information memory storing the mode information, and one of the programmable logic circuit function and the programmable wiring circuit function may be selectively made effective according to the mode information stored in the mode information memory. Each of a plurality of the base cells connected for forming the programmable logic LSI may be connected to adjacent other base cell with a plurality of bi-directional connection lines.
It is preferred that the combined programmable circuit includes a storage element group outputting data corresponding to input data and a switch group provided corresponding to each storage element of the storage element group, when the programmable wiring circuit function is effective, one of the plurality of bi-directional connection lines is electrically connected with other bi-directional connection line by ON/OFF controlling each switch element of corresponding switch element group depending upon each storage data of the storage element group. In the alternative, the combined programmable circuit includes a storage element group outputting data corresponding to input data and a switch group provided corresponding to each storage element of the storage element group, when the programmable logic circuit function is effective, a storage data of the storage element in the storage element group designated by a signal input from one of the plurality of bi-directional connection line is output to other bi-directional connection line. The storage data of each storage element of the storage element group may be externally input.
Preferably, a bit map information designating interconnection between internal bi-directional wiring may be stored in the storage element. Also, a look-up table information for realizing predetermined logical operation may be stored in the storage element.
According to the second aspect of the present invention two-dimensional array of base cell formed by arranging a plurality of base cells set forth above in two-dimensional array and connecting respectively adjacent base cells with a plurality of bi-directional connection lines.
In the construction set forth above, each of the base cell in the two-dimensional array may be connected with four base cells adjacent in upward, downward, leftward and right ward direction. In the alternative, each of the base cell in the two-dimensional array may be connected with adjacent eight base cells arranged therearound.
In further preferred construction, all of the mode information memory within each of the base cell in the two-dimensional array may be serially connected in daisy chain, and the mode information is externally input in sequential order.